JPH0427702B2 - - Google Patents

Info

Publication number
JPH0427702B2
JPH0427702B2 JP57085726A JP8572682A JPH0427702B2 JP H0427702 B2 JPH0427702 B2 JP H0427702B2 JP 57085726 A JP57085726 A JP 57085726A JP 8572682 A JP8572682 A JP 8572682A JP H0427702 B2 JPH0427702 B2 JP H0427702B2
Authority
JP
Japan
Prior art keywords
film
insulating film
etching
groove
resistant mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57085726A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58202545A (ja
Inventor
Akira Kurosawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP57085726A priority Critical patent/JPS58202545A/ja
Priority to US06/495,483 priority patent/US4497108A/en
Priority to DE8383302856T priority patent/DE3380652D1/de
Priority to EP83302856A priority patent/EP0095328B1/en
Publication of JPS58202545A publication Critical patent/JPS58202545A/ja
Publication of JPH0427702B2 publication Critical patent/JPH0427702B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
JP57085726A 1982-05-21 1982-05-21 半導体装置の製造方法 Granted JPS58202545A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP57085726A JPS58202545A (ja) 1982-05-21 1982-05-21 半導体装置の製造方法
US06/495,483 US4497108A (en) 1982-05-21 1983-05-17 Method for manufacturing semiconductor device by controlling thickness of insulating film at peripheral portion of element formation region
DE8383302856T DE3380652D1 (en) 1982-05-21 1983-05-19 Method for manufacturing semiconductor device by controlling thickness of insulating film at peripheral portion of element formation region
EP83302856A EP0095328B1 (en) 1982-05-21 1983-05-19 Method for manufacturing semiconductor device by controlling thickness of insulating film at peripheral portion of element formation region

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57085726A JPS58202545A (ja) 1982-05-21 1982-05-21 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS58202545A JPS58202545A (ja) 1983-11-25
JPH0427702B2 true JPH0427702B2 (en]) 1992-05-12

Family

ID=13866845

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57085726A Granted JPS58202545A (ja) 1982-05-21 1982-05-21 半導体装置の製造方法

Country Status (4)

Country Link
US (1) US4497108A (en])
EP (1) EP0095328B1 (en])
JP (1) JPS58202545A (en])
DE (1) DE3380652D1 (en])

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4615746A (en) * 1983-09-29 1986-10-07 Kenji Kawakita Method of forming isolated island regions in a semiconductor substrate by selective etching and oxidation and devices formed therefrom
US4603468A (en) * 1984-09-28 1986-08-05 Texas Instruments Incorporated Method for source/drain self-alignment in stacked CMOS
US4972251A (en) * 1985-08-14 1990-11-20 Fairchild Camera And Instrument Corp. Multilayer glass passivation structure and method for forming the same
US4909897A (en) * 1986-06-17 1990-03-20 Plessey Overseas Limited Local oxidation of silicon process
JPH02500872A (ja) * 1987-08-17 1990-03-22 プレツシー　オーバーシーズ　リミテツド 珪素の局部的酸化法
FR2620861B1 (fr) * 1987-09-22 1990-01-19 Schiltz Andre Procede de realisation d'isolement lateral a structure plane
EP0309788A1 (de) * 1987-09-30 1989-04-05 Siemens Aktiengesellschaft Verfahren zur Erzeugung eines versenkten Oxids
JP2742432B2 (ja) * 1988-11-25 1998-04-22 株式会社日立製作所 半導体装置の製造方法
US5387540A (en) * 1993-09-30 1995-02-07 Motorola Inc. Method of forming trench isolation structure in an integrated circuit
US6097072A (en) * 1996-03-28 2000-08-01 Advanced Micro Devices Trench isolation with suppressed parasitic edge transistors
US5721448A (en) * 1996-07-30 1998-02-24 International Business Machines Corporation Integrated circuit chip having isolation trenches composed of a dielectric layer with oxidation catalyst material
KR100226736B1 (ko) * 1996-11-07 1999-10-15 구본준 격리영역 형성방법
TW580581B (en) * 1998-11-10 2004-03-21 Mosel Vitelic Inc Method of estimating thin-film thickness and formation conditions

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4104086A (en) * 1977-08-15 1978-08-01 International Business Machines Corporation Method for forming isolated regions of silicon utilizing reactive ion etching
JPS55153342A (en) * 1979-05-18 1980-11-29 Fujitsu Ltd Semiconductor device and its manufacture
JPS56138938A (en) * 1980-03-31 1981-10-29 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device
EP0055521B1 (en) * 1980-11-29 1985-05-22 Kabushiki Kaisha Toshiba Method of filling a groove in a semiconductor substrate
US4407851A (en) * 1981-04-13 1983-10-04 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing semiconductor device

Also Published As

Publication number Publication date
EP0095328B1 (en) 1989-09-27
EP0095328A3 (en) 1986-08-20
US4497108A (en) 1985-02-05
DE3380652D1 (en) 1989-11-02
JPS58202545A (ja) 1983-11-25
EP0095328A2 (en) 1983-11-30

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